A digital Phase Locked Loop (PLL) circuit includes a digital phase comparator, a digital loop filter, a DA converter, a voltage controlled oscillator, a divider, and a phase count clock generator. The digital phase comparator receives a phase count clock from the phase count clock generator and also receives a master clock (reference clock) from an external clock source and a slave clock (divisional clock) from the divider. The digital phase comparator counts a phase difference between the master clock and the slave clock as the number of pulses of the phase count clock. A count value indicating the phase difference is subjected to time averaging by the digital loop filter, and the count value after the averaging is converted by the DA converter into an analog voltage. The voltage controlled oscillator oscillates a clock signal of a frequency in accordance with the analog voltage. The oscillated clock signal is divided by the divider at a certain divisional ratio, and the divisional clock signal is applied to the digital phase comparator as the slave clock. Through a feedback control, the oscillated clock signal of the voltage controlled oscillator is controlled so that the frequency of the master clock becomes substantially equal to the frequency of the slave clock and also the phases have a certain phase relationship.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2004-343724, Japanese National Publication of International Patent Application No. 2006-518151, or the like.